The present invention relates to circuits utilizing the Josephson effect and, more particularly, to such a logic gate which has a very short gate delay time and a wide operational margin and which is feasible for a high degree of integration.
Various kinds of logic gates have been proposed using Josephson junctions to take advantage of their low power dissipation and high switching speeds. For example, refer to the paper, "Josephson-Logic Devices and Circuits" by TUSHAR R. GHEEWALA, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 10, OCTOBER 1980, PP 1857-1869. The basic construction of the logic gate is of the interference type, consisting of a plurality of Josephson junctions and inductances adapted to electrically connect the Josephson junctions. An input current is directly injected into the logic gate or electromagnetically coupled with a control line of the logic gate, thereby switching the gate to the voltage state. T. R. Gheewala describes in his paper "Josephson logic circuits based on nonlinear current injection in interferometer devices", Applied Physics Letter, Vol. 33, No. 8, pp. 781-783, a Josephson logic gate which is designed for wider margins and higher switching speeds. FIG. 3(a) in page 782 of this paper shows an AND gate equipped with an interferometer gate having two Josephson junctions having critical currents I.sub.01 and I.sub.02, respectively, and a series connection of inductances L.sub.1 and L.sub.2 having inductance values L.sub.1 ' and L.sub.2 '. The Josephson junctions are connected in parallel by the series connection of the inductances. One input I.sub.a is coupled to the node between the inductances L.sub.1 and L.sub.2 and the other I.sub.b to one end of the inductance L.sub.1. To optimize the operation (operational margins) of this gate, the inductance values L.sub.1 ' and L.sub.2 ' and the critical currents I.sub.01 and L.sub.02 are chosen to satisfy equations: EQU L.sub.1 'I.sub.01 =L.sub.2 'I.sub.02 ( 1) EQU I.sub.02 (L.sub.1 '+L.sub.2 ')=.phi..sub.0 ( 2)
where .phi..sub.0 indicates a natural constant called "magnetic flux quantum" and having a value of the order of 2.07 pH.mA. However, the logic gate as described above is disadvantageous in various respects. Although the critical current should be small in order to reduce the power dissipation, the current I.sub.02 and the inductance values L.sub.1 ' and L.sub.2 ' cannot be reduced at the same time as seen from the equation (2) so that a large chip area is required to attain this lower power dissipation. Since the gate includes both inductances and Josephson junction capacitance, a resonance phenomena is caused which should be damped for high speed operations. Furthermore, a gate of this kind tends to trap stray magnetic fields when switching to its superconducting state; the trapped magnetic fields can cause the gate to malfunction. These problems exist not only in the above-described AND gate but in all logic gates of the interference type.
U.S. Pat. No. 4,275,314 discloses an AND gate which attempts to eliminate the above-described drawbacks by not providing with an inductance component. The AND gate, as shown in FIG. 3 of this U.S. Pat. specification, uses the circuit indicated in FIG. 1 (named JAWS) as a one-input OR gate and cascades two such OR gates. When one input is supplied to the first stage JAWS, the bias current fed to the first stage JAWS is coupled to the second stage JAWS as the second bias current. When the other signal arrives at the second stage JAWS, the second bias current is steered to the output side. This type of logic gate, although free from the drawbacks inherent in the AND gate previously described due to the absence of inductance component, nonetheless possesses several disadvantageous characteristics. First, the cascaded JAWS result in a high degree of intricacy in the circuit construction. Second, the input sensitivity, i.e., the ratio of the input current to the minimum amount of current necessary to switch the device, is as small as 1, which makes the overdrive capability relatively small. This reduction in overdrive capability reduces the ability of the gate to speed up the switching action (i.e. shorten the turn-on delay time of the gate). In more detail, an output of a gate using Josephson junctions generally appears (with a time constant of a load resistance R.sub.L and a Josephson junction capacitance C) upon the lapse of a turn-on delay time after an input current has exceeded a threshold for the circuit operation. The turn-on delay time decreases inversely with respect to the overdrive capability defined by (I.sub.0 -I.sub.th)/I.sub.0 where I.sub.0 is the input current and I.sub.th the threshold current for a predetermined gate current, as described in TURN-ON DELAY OF JOSEPHSON INTERFEROMETER LOGIC DEVICES, IEEE TRANSACTIONS ON MAGNETICS, VOL. MAG-15, NO. 1, JANUARY 1979, pp. 562-565. Obviously, the overdrive capability increases with the input sensitivity which is defined by an inclination of a control characteristic line of the gate while the turn on delay time decreases as the input sensitivity becomes higher. Thus, it is desirable to make the input sensitivity as high as possible in order to speed up the switching actions of the gate by shortening the turn-on delay time. As previously mentioned, the input sensitivity of the above-mentioned gate is 1 which is relatively low sensitivity to promote high speed switching.
Using the interferometer gate already discussed, a logic gate can be constructed having two or more input lines, and producing an output when input currents flow through a predetermined number or more of the input lines, (e.g., a 2/3 logic gate can be produced in which an output appears when input currents flow through two or more of three input lines). In the 2/3 logic gate, for instance, a gate current is constantly fed to the Josephson junctions J.sub.1 and J.sub.2 through the inductances L.sub.1 and L.sub.2 of the interferometer gate, respectively, and the critical currents are selected such that the gate switches in response to the flow of input currents through two or more of the three input lines.
With this construction, however, not only do the previously described problems remain unsolved, but the input current margins are narrow and it is difficult to realize a highly integrated circuit. More specifically, supposing that the minimum input current necessary for switching a gate under the supply of a gate current is I.sub.t, the range (margins) of the input current I.sub.in required for operation of the 2/3 logic gate is quite narrow (e.g., between I.sub.t /2 and I.sub.t). With respect to actual production, however, the input current margins will be still narrower in view of the lack of uniformity of critical current and inductance among integrated circuits. Moreover, the need for three input lines for magnetic coupling in the gate cannot be met without rendering the device design quite difficult since it is hard to equalize the degrees of magnetic coupling between the input lines and the inductances. These problems also exist in multi-input AND gates.